We present drain and source-centric design optimizations of a linear P-top and dual-channel conduction path LDMOS
(lateral double-diffused metal-oxide semiconductor) structure for low specific on-resistance (Ron.sp) powered transistor devices. The
design was simulated using TCAD tools, and a real silicon device was fabricated successfully in accordance with the simulation. The
3D effect in the cylindrical layout with the linear P-top doping profiles was designed using an analytical model to obtain optimal
charged balance for the drain- and source-centric regions. The silicon result, with an optimized P-top doping process window, achieved
a breakdown voltage (BV) of 842 V, which was higher than 800 V. Thus, the use of a dual-channel conduction path technique with an
N-top layer implanted over the P-top can improve Ron.sp by 25% without compromising BV.