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    ASIA unversity > 資訊學院 > 資訊工程學系 > 博碩士論文 >  Item 310904400/11423

    Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/11423

    Title: 高電阻N-漂移區LDMOS元件的可靠性研究
    Authors: 蔡旻縉
    Contributors: Department of Computer Science and Information Engineering
    Keywords: 衝擊游離;崩潰電壓;導通電阻;橫向擴散金屬氧化電晶體;場板;電腦輔助設計模擬
    Date: 2011
    Issue Date: 2011-09-18 19:10:36 (UTC+8)
    Publisher: Asia University
    Abstract: 這篇文章提供一個方法去顯著的改善高電阻N型漂移區LDMOS元件的崩潰電壓和導通電阻, 利用源極電極下的PBL濃度和延伸閘極場板的長度 .PBL的目的是在減少藉由衝擊游離產生的基極電流的大小, 延伸的閘極場板將會把衝擊游離區從接近閘極端的N型漂移區表面移動到 P-body和 N型漂移區之間的接面. 由於N型漂移區的最大空乏區增加,因此崩潰電壓也跟著增加.
    Appears in Collections:[資訊工程學系] 博碩士論文

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