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    Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/16769


    Title: Development Pattern Recognition Model for Classification of Circuit Probe Wafer Maps on Semiconductors
    Authors: 洪炯宗;Horng, Jorng-Tzong;葉榮輝;Yeh, Rong-Hwei
    Contributors: 生物與醫學資訊學系
    Keywords: semiconductor wafer classification;circuit probe test;features extraction;Hough transform;data mining
    Date: 2012-08
    Issue Date: 2012-11-23 17:16:48 (UTC+8)
    Abstract: Circuit probe test is an end of line testing that the individual die has been measured at wafer level in modern semiconductor manufacturing. The test results are visualized as a spatial distribution of the failures on the wafer which can provide some valuable information for the production of failures. In order to reduce time consumption by human operation, a great accuracy of automatic classification system is clear needed for engineering analysis. In this paper, we demonstrate how a robust feature extraction procedure using by classical Hough transform (HT) and circular Hough transform (CHT) can be adapted to detect lines and rounds spatial patterns on circuit probe wafer map. In addition, we also used several technique to detect others spatial patterns. These features which are effectively eliminate the influence of noise to perform pattern classification. The presented methodology is validated with real fabrication data and several data mining classification algorithms are presented to evaluate the advantage of this methodology.
    Relation: IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES
    Appears in Collections:[生物資訊與醫學工程學系 ] 期刊論文

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