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    ASIA unversity > 資訊學院 > 資訊工程學系 > 期刊論文 >  Item 310904400/18620

    Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/18620

    Title: Variaton of Lateral Thickness techniques in SOI Lateral High Voltage Transistors
    Authors: 郭宇鋒;Guo, Yufeng;王至剛;Wang, Zhigong;許健;Sheu, Gene
    Contributors: 資訊工程學系
    Date: 2009-07
    Issue Date: 2012-11-26 13:56:04 (UTC+8)
    Abstract: A novel variation of Lateral Thickness(VLT) technique is proposed to bring a uniform surface electric field of SOl lateral high voltage devices. Comparing to the conventional RES URF device, the linear thickness of drift region increases the breakdown voltage by 40% while decreasing the drift resistance by 50%. Furthermore, single- or two-step drift thickness can be adopted to reduce fabrication difficulties when higher breakdown voltage and lower drift resistance are maintained.
    Relation: 2009 International Conference on Communications, Circuits and Systems (ICCCAS2009)
    Appears in Collections:[資訊工程學系] 期刊論文

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