In this paper, we propose a method for depositing the charge trapping layer of a high-k polySi-SiO2-ZrO2-SiO2-Si (SOZOS) memory device. In this approach, the trapping layer was formed through simple two steps: (i) spin-coating of the ZrCl4 precursor and (ii) rapid thermal annealing for 1 min at 900 C under an oxygen atmosphere. The morphology of the ZrO2 charge trapping layer was confirmed through X-ray photoemission spectroscopy analysis. The sol-gel-derived layer exhibited improved charge trapping in the SOZOS memory device, resulting in a threshold voltage shift of 2.7 V in the I-d-V-g curve, P/E (program/erase) speeds as fast as 0.1 ms, good data retention up to 10(4) s (only a 5% charge loss due to deep trapping in the ZrO2 layer), and good endurance (no memory window narrowing after 10(5) P/E cycles). (c) 2006 The Electrochemical Society.