In recent years, the power devices become more and more important due to the big demands for liquid crystal display (LCD), electrical plasma display, LED, and communication products. It is a future trend that power devices and low voltage will be integrated on the same chip; however, one of very important power devices is LDMOS. It is often unable to simulate devices with special layouts such as Racetracks and Fingers, and so in this thesis it focuses on 3D simulations of power device LDMOS by using Sentaurus tool. The 3D simulation results of power device LDMOS of Power Device shows serious Current Crowding Effects which the traditional 2D simulation is unable to achieve. There are two methods to reduce Current Crowding Effects of LDMOS. The first method is to change Nd doping density which can change the electrical fields near the Drain end and Field Plate end and further improve the Current Crowding Effects. The second method is to increase rN width can change the electric fields near Drain end ; when the rN width increases, the electrical field near the drain end will reduce so that the Current Crowding Effects will be improved. By simulations of buried P-top LDMOS devices in this thesis, it is found that the Nd doping density can be increased with compensation of buried P-top dose to reduce Ron and achieve the optimized design of LDMOS devices.