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    Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/4718


    Title: An intelligent parallel loop for parallelizing compilers
    Authors: Yun-Woei Fann;Chao-Tung Yang;S. S. Tseng;Chang-Jiun Tsai
    Contributors: Department of Information Science and Applications
    Keywords: parallelizing compiler;parallel loop scheduling;knowledge-based system;multiprocessor systems;speedup
    Date: 2000-03
    Issue Date: 2009-11-30 16:03:15 (UTC+8)
    Publisher: Asia University
    Abstract: In this paper we propose a knowledge-based approach to solving loop-scheduling problems. A rule-based system, called IPLS, is developed by combining a repertory grid and an attribute ordering table to construct a knowledge base. IPLS chooses an appropriate scheduling algorithm by inferring some features of loops and assigning parallel loops to multiprocessors to achieve significant speedup. Because more attributes are proposed, the accuracy of selection of an appropriate scheduling method is improved. In addition, the refined IPLS system can automatically adjust the attributes in the knowledge base according to profile information; therefore, IPLS has the capability of feedback learning. The experimental results show that our approach can achieve greater speedup on multiprocessor systems than can others.
    Relation: Journal of Information Science and Engineering 16(2):169- 200
    Appears in Collections:[行動商務與多媒體應用學系] 期刊論文

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