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    Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/4780

    Title: Parallel Evalutation Model for Software Architecture Specification
    Authors: Jeffrey J. P. Tsai;B. Li;E. Juan
    Date: 1997-01
    Issue Date: 2009-12-02 09:04:10 (UTC+8)
    Publisher: Asia University
    Abstract: The concept of software architecture has recently emerged as a new way to improve our ability to effectively construct large scale software systems. This article presents a hybrid parallel evaluation model using a logic-based architecture specification language to speed up these processes. This model can preserve maximum parallelism while guaranteeing to generate all solutions of a logic-based architecture specification without backtracking. The power of this model comes from the fact that the static data dependency is capable of representing all evaluation sequences and all multiple solutions implied by a logic-based architecture specification. Simplified synchronization data structure used in our approach reduces the complexity of current approaches according to the hybrid evaluation model. Specifically, the duration of the synchronization data structures and their complexity can be reduced. The model is guaranteed to find the maximum degree of AND, and OR, parallelism. The model can eliminate backtracking structure from the evaluation control structure.
    Relation: Communications of the ACM 40(1):83-86
    Appears in Collections:[生物資訊與醫學工程學系 ] 期刊論文

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