Speeding up verification is a significant issue on development of FPGA systems. During pre-simulation phase, the simulator only generates stimulus and response with behavior of circuits. However, simulation and debugging steps in designing a complex system require extremely long and time-consuming test sequences. In this work, we propose an efficient verification method to automatically verify between golden data and simulation results on bus transaction in FPGA systems. Additionally, we also develop and integrate an enhanced FPGA verification tool with graphic user interface to verify user’s design. Finally, a simple CPU design example will be demonstrated to show the feasibility of proposed tool.