ASIA unversity:Item 310904400/5773
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    ASIA unversity > 資訊學院 > 會議論文 >  Item 310904400/5773


    jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://asiair.asia.edu.tw/ir/handle/310904400/5773


    题名: Design of Automatic Timing Verification Tool for FPGA Systems
    作者: Trong-Yen Lee;Chou-Chuan Yao;Yang-Hsin Fan;Chia-Chun Tsai;Rong-Shue Hsiao
    贡献者: National Taipei University of Technology;National Taitung University;Nanhua University
    关键词: FPGA system;Bus transaction;Timing verification
    日期: 2007-12-20
    上传时间: 2009-12-15
    出版者: 亞洲大學資訊學院;中華電腦學會
    摘要: Speeding up verification is a significant issue on development of FPGA systems. During pre-simulation phase, the simulator only generates stimulus and response with behavior of circuits. However, simulation and debugging steps in designing a complex system require extremely long and time-consuming test sequences. In this work, we propose an efficient verification method to automatically verify between golden data and simulation results on bus transaction in FPGA systems. Additionally, we also develop and integrate an enhanced FPGA verification tool with graphic user interface to verify user’s design. Finally, a simple CPU design example will be demonstrated to show the feasibility of proposed tool.
    關聯: 2007NCS全國計算機會議 12-20~21
    显示于类别:[資訊學院] 會議論文

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