ASIA unversity:Item 310904400/5777
English  |  正體中文  |  简体中文  |  Items with full text/Total items : 90120/105277 (86%)
Visitors : 8144250      Online Users : 2040
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    ASIAIR > College of Computer Science > Proceedings >  Item 310904400/5777


    Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/5777


    Title: Front-End Policy based on Speculation Condition for Simultaneous Multithreading Architecture
    Other Titles: 以投機狀況為基礎的同步多線程架構前端策略
    Authors: 陳沛源;謝忠健
    Contributors: 大同大學資訊工程所
    Keywords: 同步多線程架構;提取策略;投機執行;Simultaneous Multithreading Architecture;Fetch policy;Speculative Execution
    Date: 2007-12-20
    Issue Date: 2009-12-15
    Publisher: 亞洲大學資訊學院;中華電腦學會
    Abstract: 對現代能夠進行多重發送的超純量處理器而言,指令提取單元是讓高效力的執行單元能夠保持全速運作的關鍵之一。用以評價指令提取單元的數據不只有發送指令的速率還有投機執行的準度。也就是說一個好的指令提取單元要能在合理的時脈時間內,從正確的執行路徑上擷取大量的指令。在同步多線程架構的處理器上狀況會有些許的不同,因為在處理器中同時有多個活動中的程序。若是能得知每個線程未來的投機執行狀況,前端的指令提取單元可以偏好具有高度可預測性執行路徑的執行緒,以避免誤入錯誤執行路徑時額外產生的資源及電力浪費。在本論文中,我們將焦點擺在改善同步多線程處理器的前端執行單元。我們提出了一個輔助性的結構稱作Sequential Trace Table (STT) ,來提供對各個執行緒投機執行狀況的預先觀察。並利用這些投機執行狀況的資訊以輔助排定提取優先權的策略。For modern wide-issue superscalar processors, high performance instruction fetch unit is the key component to keep the powerful execution engine operating in full speed. The performance measurement to evaluate a front-end mechanism includes both the instruction delivery rate and
    speculation accuracy. That means a good front-end engine should be able to fetch and dispatch massive instructions on the right execution path, in a reasonable clock cycle time. Things may be a little different in Simultaneous Multithreading (SMT) architecture because there are multiple active contexts inside the CPU. If we can extract some information about future speculation conditions of each thread, the front-end fetch engine can then prefer threads with highly predictable execution path to avoid resource or energy waste on mis-speculative routes. In this paper, we focus on improving the frontend engine of SMT processor. We present a supplementary structure called Sequential Trace Table (STT) to provide a look-ahead into the future speculating conditions of each thread, and use the information to help improving fetch prioritizing policies.
    Relation: 2007NCS全國計算機會議 12-20~21
    Appears in Collections:[College of Computer Science] Proceedings

    Files in This Item:

    File SizeFormat
    1019.pdf277KbAdobe PDF362View/Open


    All items in ASIAIR are protected by copyright, with all rights reserved.


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback