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    ASIA unversity > 資訊學院 > 光電與通訊學系 > 期刊論文 >  Item 310904400/64381


    Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/64381


    Title: Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire
    Authors: 李克慧;Ko-Hui Lee;蔡宗叡;Jung-Ruey Tsai;張睿達;Ruey-Dar Chang;林鴻志;Horng-Chih Lin;黃調元;Tiao-Yuan Huang
    Contributors: 光電與通訊學系
    Keywords: elemental semiconductors;flash memories;nanoelectronics;nanofabrication;nanowires;silicon
    Date: 2013-10
    Issue Date: 2013-11-01 10:14:42 (UTC+8)
    Abstract: A gate-all-around polycrystalline silicon nanowire (NW) floating-gate (FG) memory device was fabricated and characterized in this work. The cross-section of the NW channels was intentionally made to be triangular in shape in order to study the effects of the corners on the device operation. Our results indicate that the channel corners are effective in lowering the programming and erasing (P/E) operation voltages. As compared with the charge-trapping type devices, a larger memory window is obtained with the FG scheme under low-voltage P/E conditions. A model considering the nature of the charge storage medium is proposed to explain the above findings.
    Relation: Applied Physics Letters, Volume:103 ,Issue: 15
    Appears in Collections:[光電與通訊學系] 期刊論文

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