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    顯示項目1051-1061 / 1061. (共43頁)
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    日期題名作者
    1992 A Specification Processing Environment for Making Well Engineered Logic Programs Timothy K. Shih; Ruth Davis; Rob Langsner
    1992 Intelligence Backtracking and Controls Based on a Deduction Status Representation in Logic Programming Timothy K. Shih; Ruth Davis
    1992 Verification of Systolic Architecture Designs Fuyau Lin; Timothy K. Shih
    1992 Inductive Techniques for Formal Verification of Systolic Array Designs in DSP Applications Nam Ling; Timothy K. Shih; Jonathan Huang
    1992 Using Prolog as a Tool for Systolic Array Designs Fuyau Lin; Timothy K. Shih; Nam Lin; Ruth Davis
    1992 Disciplined Exceptions in Logic Programming, Timothy K. Shih; Ruth E. Davis; Fuyau Lin
    1992 An Automatic Design Specification and Verification Tool for Systolic Architecture Timothy K. Shih; Nam Ling; Ruth Davis; Fuyau Lin
    1991 Verification Tools for Systolic Array Design Fuyau Lin; Timothy K. Shih; Nam Ling
    1991 Axiomatic Approach for Systolic Array Design Fuyau Lin; Timothy K. Shih; Nam Ling
    1991 Automatic Formal Verification of Systolic Array Designs Nam Ling; Fuyau Lin; Timothy K. Shih; Ruth Davis
    1990 A CASE for Logic Programming R. E. Davis; Timothy K. Shih

    顯示項目1051-1061 / 1061. (共43頁)
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