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    ASIA unversity > 資訊學院 > 資訊工程學系 > 會議論文 >  Item 310904400/7778


    Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/7778


    Title: VSTA: A Prolog-based Formal Verifier for Systolic Array Designs
    Authors: Nam Ling;Timothy K. Shih
    Date: 1993
    Issue Date: 2010-01-29 15:58:37 (UTC+8)
    Publisher: Asia University
    Relation: Proceedings of The 1993 Internal Conference on Parallel Processing, U.S.A., 1993.
    Appears in Collections:[資訊工程學系] 會議論文

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