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    ASIA unversity > 資訊學院 > 資訊工程學系 > 期刊論文 >  Item 310904400/88375


    Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/88375


    Title: A 10-bit current-steering CMOS digital to analog converter
    Authors: 易昶霈;Yi, Chang-Pei
    Contributors: 資訊工程學系
    Keywords: AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
    Current-steering DAC;Digital to analog converter;DNL;INL;Segmented DAC
    Date: 2015-01
    Issue Date: 2015-03-25 15:43:31 (UTC+8)
    Abstract: This paper proposed a 10-bit digital-to-analog converter consisting of a segmented current-steering architecture, with five different sizes of current source.

    The proposed 10-bit digital-to-analog converter was implemented using TSMC CMOS 0.35 μm 2P4M technology. The power consumption was approximately 7.9 mW at the sample rate of 200 MHz, and the supply voltage was 3.3 V. It achieved a DNL (differential nonlinearity) and an INL (integral nonlinearity) of 0.16 LSB and 0.13 LSB, respectively. The measured SFDR (spurious free dynamic range) was 45.3 dB under a 1 MHz sine waveform.

    This work presented a good performance compared with other researches in DNL, INL and power consumption.
    Relation: 易昶霈;69(1): 14–17
    Appears in Collections:[資訊工程學系] 期刊論文

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