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    Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/9590


    Title: 區塊傳輸系統利用通道資訊之最佳聯合傳收機設計方法
    Authors: 吳俊賢
    Contributors: 資訊學院
    光電與通訊學系
    Keywords: 區塊傳輸系統
    前置編碼器
    冗餘資料量
    區塊延遲
    聯合設計
    傳收機
    區塊內決策回授等化器
    block transmissions
    precoder
    redundancy
    block delay detection
    joint design,
    transceiver
    intrablock decision feedback equalizer
    Date: 2009
    Issue Date: 2010-05-12 14:16:16 (UTC+8)
    Abstract: 本計劃擬針對區塊傳輸通訊系統在獲得通道資訊下,建立傳送機與具區塊延遲偵測
    接收機之聯合設計架構。我們將分別探討接收機使用線性等化方式與非線性之區塊內決
    策回授等化方式。文獻上,無論是針對單天線或多天線通訊系統,單區塊基底的傳送機
    與接收機的聯合設計,大都是建立在給定一個通道矩陣的情況下;而這一通道矩陣常假
    設是平坦性衰落或是等效平坦性衰落(即在區塊間插入足夠冗餘資料量,轉化頻率選擇
    性衰落通道為平坦性衰落通道)。最近,我們提出一個基於斜投影為架構的串接式等化
    機制,在迫零等化條件下,設計一滿足最低平均位元錯誤率的單區塊基底編碼器。此架
    構的優點,在於可針對區塊傳輸系統在不足冗餘資料量下,聯合設計一單區塊基底前置
    編碼器與其接收機。本計畫係考慮系統區塊延遲偵測為一設計變數,並提出新的完整設
    計方案來聯合設計傳收機。本計畫擬分兩年期完成,每一年的研究目標說明如下。
    在計畫執行的第一年,我們將建立一個新的架構來聯合設計一個線性傳送機與線性
    接收機系統。利用所提架構,在有限傳送功率條件下,我們將設計一個最佳單區塊基底
    前置編碼器與具有最佳系統區塊延遲之串接式等化器,使系統平均位元錯誤率達最小
    值。我們將研究區塊內使用迫零與最小均方誤差兩等化準則的性能表現,並分別建立能
    達成最低錯誤率之最佳區塊延遲確立演算法。在計畫執行的第二年,我們將針對非線性
    接收機的傳收機,建立聯合設計的方法。特別地,我們將設計一個新型的區塊內決策回
    授等化器。此新型等化器的饋前等化路徑,將採用第一年所研製的具區塊延遲之串接式
    等化器。於是,在有限傳送功率條件下,我們將設計一個最佳單區塊基底前置編碼器與
    具有最佳系統區塊延遲之區塊內決策回授等化器,使系統平均位元錯誤率可達最低。同
    樣地,對此新型區塊內決策回授等化器,我們也將研究區塊內使用迫零與最小均方誤差
    兩等化準則的性能表現,並分別建立能達成最低錯誤率之最佳區塊延遲確立演算法。要
    特別說明的是,不同於過去文獻的研究,本兩年期計畫所擬研製的聯合傳收機設計方
    法,將一併考慮區塊傳輸系統具有「足夠」冗餘資料量及「不足夠」冗餘資料量兩種情
    況。
    This project is to develop the frameworks for jointly designing the transmitter and
    receiver with block delay detection for block transmission systems with channel state
    information. The receivers using linear and nonlinear intrablock decision feedback
    equalization are investigated. For a single antenna or multiple antennas communication
    system, in the literature the block-based transmitter-receiver pair is jointly designed for a
    given channel matrix, which is usually assumed flat-fading or equivalent flat-fading (i.e.,
    translated from a frequency-selective fading channel by inserting sufficient redundancy
    between blocks). Recently, a cascaded equalizing scheme, based on the oblique projection, is
    proposed by us to devise a minimum bit-error-rate(BER) block-based precoder with
    zero-forcing (ZF) equalization. The merit of the proposed framework is that it enables the
    joint design of a block-based precoder and the linear receiver for block transmissions with
    insufficient redundancy. In this project, a complete method for jointly designing the
    transceiver is pursued when the system block delay is considered being a design variable. The
    project is divided into two-year terms and the goal for each year is described as follows.
    In the first year, a novel framework is developed for jointly designing a linear transmitter
    and a linear receiver. In such a framework, an optimum block-based precoder and a cascaded
    equalizer with optimum block delay detection are devised such that the average BER is
    minimized, subject to the transmission power constraint. The algorithms of determining the
    optimum block delay of the cascaded equalizer for minimizing BER are built for intrablock
    ZF and minimum mean square error (MMSE) equalization, respectively. In the second year, a
    nonlinear receiver is considered in the joint design of the transceiver. Particularly, a novel
    intrablock decision feedback equalizer (IDFE) is devised by applying the proposed cascaded
    equalizing structure with block delay in the feedforward equalizing path. Consequently, we
    design an optimum block-based precoder and an intrablock decision feedback equalizer with
    optimum block delay detection such that the average BER is minimized, subject to the
    transmission power constraint. The algorithms of determining the optimum block delay of the
    proposed IDFE for minimizing BER are also developed for intrablock ZF and MMSE
    equalization, respectively. Contrary to previous studies, the cases of using sufficient and
    insufficient redundancy for block transmissions are addressed in this project for the joint
    design of the transceiver.
    Appears in Collections:[光電與通訊學系] 科技部研究計畫

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